Project Trellis

Project status: Unknown

Maps the architecture and configuration bitstream of Lattice ECP5 FPGAs, supplying device information and tools for independent FPGA development.

Target software or hardware: Lattice ECP5 FPGA bitstreams
Original platform: Lattice ECP5
Work type: Reverse engineering and documentation
Primary public repository: github.com/yosyshq/prjtrellis

GitHub

Votes express community demand, not project progress or quality.

About and scope

Project Trellis studies the ECP5 bitstream and internal architecture using an experimental documentation process. Its tools and device database connect that research to an open FPGA development flow. The effort has a specific ECP5 scope, distinct from IceStorm's iCE40 research.

Contribution availability

Contribution policy unknown

AI-assisted contribution policy: Unspecified

Documented contributor systems

Contributor setup not documented

Reported progress

Progress not reported

Sources, builds and releases

Open repository · github.comgithub.com/yosyshq/prjtrellis